As memory devices of all types have evolved, continuous strides have been made in improving their performance in a variety of respects. For example, the storage capacity of memory devices has continued to increase at geometric proportions. This increased capacity, coupled with the geometrically higher operating speeds of electronic systems containing memory devices, has made high memory device bandwidth ever more critical useful. One application in which memory devices, such as dynamic random access memory (“DRAM”) devices, require may benefit from a higher bandwidth is their use as system memory in computer systems. As the operating speed of processors has increased, processors are able to read and write data at correspondingly higher speeds. Yet conventional DRAM devices often sometimes do not have the bandwidth to read and write data at these higher speeds, thereby slowing the performance of conventional computer systems. This problem is exacerbated by the trend toward multi-core processors and multiple processor computer systems.
High Bandwidth Memory (HBM) systems represent another step in the evolution of memory devices that attempt to allow the use of a conventional DRAM device and yet achieve high-bandwidth memory access. In general, HBM systems access a stack of DRAM devices using multiple channels that can interface with respective DRAM locations independent of other channels. In some HBM systems, the independent operable channels can accommodate overlapping communications that can give rise to asynchronous noise between the channels that can negatively affects the operation of the HBM system. Present test apparatus and methods can identify certain constraints of an HBM system, such as damaged memory cells, but do not provide any guidance with respect to failures associated with identify channel interference issues.